//Jeff Szcinski & KQBright
//Lab 2
//ECEN 4243
//Spring 2014

module alupipe (dbus, abus, bbus, Cin, S, clk); //final version 
	output [31:0] dbus;
	input [31:0] abus, bbus;
	input Cin, clk;
	input [2:0] S;
	
	
	wire Cout, V;
	wire [31:0] c, g, p; 
	wire gout, pout; 
	wire [31:0] aout, bout, din;
	
	
	ClkReg32 clkA(
		.Q(aout),
		.D(abus),
		.clk(clk)
	);
	
	ClkReg32 clkB(
		.Q(bout),
		.D(bbus),
		.clk(clk)
	);
	
	ClkReg32 clkD(
		.Q(dbus),
		.D(din),
		.clk(clk)
	);
	
	Alu_cell cell1[31:0] ( 
		.d(din), 
		.g(g), 
		.p(p), 
		.a(aout), 
		.b(bout), 
		.c(c), 
		.S(S) 
	); 
	
	Lac5 lac ( 
		.c(c), 
		.gout(gout), 
		.pout(pout), 
		.Cin(Cin), 
		.g(g), 
		.p(p) 
	); 
	
	assign Cout = gout | (pout & Cin); 
	assign V = Cout ^ c[31]; 
endmodule